Details

Autor(en) / Beteiligte

• Akinwande, A.I.
• MacTaggart, I.R.
• Betz, B.K.
• Grider, D.E.
• Lange, T.H.
• Nohava, J.C.
• Tetzlaff, D.E.
• Arch, D.K.

Titel

A 500-MHz 1616 complex multiplier using self-aligned gate GaAs heterostructure FET technology

Ist Teil von

• IEEE journal of solid-state circuits, 1989-10, Vol.24 (5), p.1295-1300

Ort / Verlag

IEEE

Erscheinungsjahr

1989

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• A 16*16-bit complex multiplier using self-aligned gate GaAs heterostructure FET technology has been demonstrated. The multiplier uses a modified Booth's algorithm and three stages of pipeline with an embedded accumulator to allow the computation of a complex multiply function. A total of 4500 gates and over 20000 devices are required to implement this function and self-test functions. The chip produces a 20-bit output allowing 40 bits to describe a complex number result. Direct coupled NOR-gate FET logic was used throughout. The complex multiplier operated at a clock rate of 520 MHz with a power dissipation of 4 W under self-test. This corresponds to an average 'loaded' gate delay of 96 ps at 0.89 mW/gate. It also means that the multiplier produces a complex product, generated using four real multiplications and two additions, in less than 8 ns. This result demonstrates the high-speed capability of LSI digital circuits fabricated using MBE-grown GaAs heterostructure FET technology.< >