Details

Autor(en) / Beteiligte

• Lu, N.C.-C.
• Bronner, G.B.
• Kitamura, K.
• Scheuerlein, R.E.
• Henkels, W.H.
• Dhong, S.H.
• Katayama, Y.
• Kirihata, T.
• Niijima, H.
• Franch, R.L.
• Wang, W.
• Nishiwaki, M.
• Pesavento, F.L.
• Rajeevakumar, T.V.
• Sakaue, Y.
• Suzuki, Y.
• Iguchi, Y.
• Yano, E.

Titel

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

Ist Teil von

• IEEE journal of solid-state circuits, 1989-10, Vol.24 (5), p.1198-1205

Ort / Verlag

New York, NY: IEEE

Erscheinungsjahr

1989

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• Describes a 1-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address multiplexing. A double-polysilicon double-metal CMOS technology having PMOS arrays inside n-wells was developed with an average 1.3- mu m feature size. The chip has also been fabricated in a 0.9*shrunken version with an area of 67 mm/sup 2/, showing a 22-ns access time. The chip power consumption is lower than 500 mW at 60-ns cycle time. This HSDRAM, which provides SRAM-like speed while retaining DRAM-like density, allows DRAMs to be used in a broad new range of applications.< >