2010 Proceedings of ESSCIRC, 2010, p.218-221
2010
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- Autor(en) / Beteiligte
- Titel
- An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H
- Ist Teil von
- 2010 Proceedings of ESSCIRC, 2010, p.218-221
- Ort / Verlag
- IEEE
- Erscheinungsjahr
- 2010
- Quelle
- IEEE Electronic Library Online
- Beschreibungen/Notizen
- An 11b 60MS/s 2-channel two-step SAR ADC in 65nm CMOS is presented. The scheme shares the op-amp between channels for the residual generation and takes advantage of time interleaving for reusing the input S&H of the first stage. A reduction of the gain in the residual generator and sub-threshold operation enables the use of a power-effective, singlestage op-amp with 69dB-gain. The ADC achieves peak SNDR of 57.6dB while consuming 2.1mW from 1-V analog and 0.85-V digital supply, resulting in an FoM of 57fJ/step.
- Sprache
- Englisch
- Identifikatoren
- ISBN: 9781424466627, 1424466628ISSN: 1930-8833eISSN: 2643-1319DOI: 10.1109/ESSCIRC.2010.5619890Titel-ID: cdi_ieee_primary_5619890
- Format
- –
- Schlagworte
- Accuracy, Arrays, Clocks, CMOS integrated circuits, Generators, Timing, Transistors