Sie befinden Sich nicht im Netzwerk der Universität Paderborn. Der Zugriff auf elektronische Ressourcen ist gegebenenfalls nur via VPN oder Shibboleth (DFN-AAI) möglich. mehr Informationen...
An 8.5-Gb/s single-chip optoelectronic integrated circuit (OEIC) for short-distance optical communications is realized in a 0.13-μm CMOS process. The OEIC consists of an on-chip silicon photodiode, a transimpedance amplifier with modified regulated cascode input configuration, an adaptive equalizer based upon slope-detection algorithm, and a limiting amplifier with merged negative impedance circuits. The proposed slope-detection adaptive equalizer compensates the limited bandwidth and the temperature variation of the integrated silicon photodiode. Measured results demonstrate 120-dB Ω transimpedance gain, 5.9-GHz bandwidth, -3.2-dBm optical sensitivity for 10 -12 BER, and 47-mW power dissipation from a single 1.5-V supply. The OEIC chip core occupies the area of 0.1 mm 2 .