Details

Autor(en) / Beteiligte

• Ying-Zu Lin
• Chun-Cheng Liu
• Guan-Ying Huang
• Ya-Ting Shyu
• Soon-Jyh Chang

Titel

A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS

Ist Teil von

• 2010 Symposium on VLSI Circuits, 2010, p.243-244

Ort / Verlag

IEEE

Erscheinungsjahr

2010

Quelle

IEEE Explore

Beschreibungen/Notizen

• This paper reports a subranged SAR ADC consisting of a 3.5-bit flash coarse ADC, a 6-bit SAR fine ADC, and a differential segmented capacitive DAC. The flash ADC controls thermometer MSBs of the DAC and SAR ADC controls the binary LSBs. The segmented DAC improves DNL during MSB transitions. The merged switching of MSB capacitors enhances operation speed. The 9-bit 150-MS/s ADC consumes 1.53 mW from a 1.2-V supply. The ENOB is 8.69 bit and ERBW is 100 MHz. The FOMs at 1.2 V, 150 MS/s and 1 V, 100 MS/s are 24.7 and 17.7 fJ/conversion-step, respectively. At 1.3-V supply voltage, the sampling rate achieves 200 MS/s.