2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010, p.386-387
2010
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Details
- Autor(en) / Beteiligte
- Titel
- A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
- Ist Teil von
- 2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010, p.386-387
- Ort / Verlag
- IEEE
- Erscheinungsjahr
- 2010
- Quelle
- IEEE Xplore
- Beschreibungen/Notizen
- This paper presents a 10 b SAR ADC with a binary-scaled error compensation technique. The prototype occupies an active area of 155 × 165 ¿m 2 in 65 nm CMOS. At 100 MS/S, the ADC achieves an SNDR of 59.0 dB and an SFDR of 75.6 dB, while consuming 1.13 mW from a 1.2 V supply. The FoM is 15.5 fJ/conversion-step.
- Sprache
- Englisch
- Identifikatoren
- ISBN: 1424460336, 9781424460335ISSN: 0193-6530eISSN: 2376-8606DOI: 10.1109/ISSCC.2010.5433970Titel-ID: cdi_ieee_primary_5433970
- Format
- –
- Schlagworte
- Capacitance, Capacitors, Circuits, Clocks, CMOS technology, Error compensation, Frequency, Logic, Sampling methods, Voltage