Details

Autor(en) / Beteiligte

• Yao-Jen Lee
• Yu-Lun Lu
• Fu-Kuo Hsueh
• Kuo-Chin Huang
• Chia-Chen Wan
• Tz-Yen Cheng
• Ming-Hung Han
• Kowalski, J.M.
• Kowalski, J.E.
• Dawei Heh
• Hsi-Ta Chuang
• Yiming Li
• Tien-Sheng Chao
• Ching-Yi Wu
• Fu-Liang Yang

Titel

3D 65nm CMOS with 320°C microwave dopant activation

Ist Teil von

• 2009 IEEE International Electron Devices Meeting (IEDM), 2009, p.1-4

Ort / Verlag

IEEE

Erscheinungsjahr

2009

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• For the first time, CMOS TFTs of 65 nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF 2 for p-MOS TFTs and P 31 for n-MOS TFTs at a low temperature of 320°C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.