Details

Autor(en) / Beteiligte

• Chang-Yun Chang
• Tsung-Lin Lee
• Wann, C.
• Li-Shyue Lai
• Hung-Ming Chen
• Chih-Chieh Yeh
• Chih-Sheng Chang
• Chia-Cheng Ho
• Jyh-Cherng Sheu
• Tsz-Mei Kwok
• Feng Yuan
• Shao-Ming Yu
• Chia-Feng Hu
• Jeng-Jung Shen
• Yi-Hsuan Liu
• Chen-Ping Chen
• Shin-Chih Chen
• Li-Shiun Chen
• Chen, L.
• Yuan-Hung Chiu
• Chu-Yun Fu
• Ming-Jie Huang
• Yu-Lien Huang
• Shih-Ting Hung
• Jhon-Jhy Liaw
• Hsien-Chin Lin
• Hsien-Hsin Lin
• Lin, L.-T.S.
• Shyue-Shyh Lin
• Yuh-Jier Mii
• Ou-Yang, E.
• Ming-Feng Shieh
• Chien-Chang Su
• Shih-Peng Tai
• Hun-Jan Tao
• Ming-Huan Tsai
• Kai-Ting Tseng
• Kin-Weng Wang
• Shiang-Bau Wang
• Xu, J.J.
• Fu-Kai Yang
• Shu-Tine Yang
• Chen-Nan Yeh

Titel

A 25-nm gate-length FinFET transistor module for 32nm node

Ist Teil von

• 2009 IEEE International Electron Devices Meeting (IEDM), 2009, p.1-4

Ort / Verlag

IEEE

Erscheinungsjahr

2009

Quelle

IEEEXplore

Beschreibungen/Notizen

• FinFET is the most promising double-gate transistor architecture to extend scaling over planar device. We present a high-performance and low-power FinFET module at 25 nm gate length. When normalized to the actual fin perimeter, N-FinFET and P-FinFET have 1200 and 915 ¿A/¿m drive current respectively at 100 nA/¿m leakage under 1V. To our knowledge this is the best FinFET drive current at such scaled gate length. This scaled gate length enables this FinFET transistor for 32 nm node insertion. With aggressive fin pitch scaling, the effective transistor width is approximately 1.9X and 2.7X over planar for typical logic and SRAM on the same layout area (i.e., silicon real estate). Due to superior electrostatics and reduced random dopant fluctuation, this high drive current can be readily traded with V DD scaling for low power.