Details

Autor(en) / Beteiligte

• Devlin, B.
• MyeongGyu, J.
• Nakura, T.
• Ikeda, M.
• Asada, K.

Titel

647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA

Ist Teil von

• 2009 Proceedings of ESSCIRC, 2009, p.156-159

Ort / Verlag

IEEE

Erscheinungsjahr

2009

Quelle

IEEE Xplore

Beschreibungen/Notizen

• We propose a self synchronous field programmable gate array (SSFPGA) with dual-pipeline (DP) architecture to eliminate pre-charge time for dynamic logic. A self synchronous LUT (SSLUT) consists of a three input tree-type structure with 8 bit SRAM for programming. A self synchronous switch box (SSSB) consists of both pass transistors and buffers. One common block with one SSLUT and one SSSB occupies 2.2lambda 2 area and the prototype SSFPGA with 34 times 30 (1020) blocks is designed and fabricated using 65 nm CMOS. Measured results show 647 MHz operation for a chain of 32 AND gates at 1.2 V and 430 MHz operation for a 3 bit ripple carry adder. Simulation results show 0.642 pJ/block/cycle operation at 647 MHz, 1.2 V.