Details

Autor(en) / Beteiligte

• Cadambi, S.
• Durdanovic, I.
• Jakkula, V.
• Sankaradass, M.
• Cosatto, E.
• Chakradhar, S.
• Graf, H.P.

Titel

A Massively Parallel FPGA-Based Coprocessor for Support Vector Machines

Ist Teil von

• 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines, 2009, p.115-122

Ort / Verlag

IEEE

Erscheinungsjahr

2009

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• We present a massively parallel FPGA-based coprocessor for Support Vector Machines (SVMs), a machine learning algorithm whose applications include recognition tasks such as learning scenes, situations and concepts, and reasoning tasks such as analyzing the recognized scenes and semantics. The coprocessor architecture, targeted at both SVM training and classification, is based on clusters of vector processing elements (VPEs) operating in single-instruction multiple data (SIMD) mode to take advantage of large amounts of data parallelism in the application. We use the FPGA's DSP elements as parallel multiply-accumulators (MACs), a core computation in SVMs. A key feature of the architecture is that it is customized to low precision arithmetic which permits one DSP unit to perform two or more MACs in parallel. Low precision also reduces the required number of parallel off-chip memory accesses by packing multiple data words on the FPGA-memory bus. We have built a prototype using an off-the-shelf PCI-based FPGA card with a Xilinx Virtex 5 FPGA and 1 GB DDR2 memory. For SVM training, we observe application-level end-to-end computation speeds of over 9 billion multiply-accumulates per second (GMACs). For SVM classification, using data packing, the application speed increases to 14 GMACs. The FPGA-based system is about 20times faster than a dual Opteron 2.2 GHz processor CPU, and dissipates around 10 W of power.