IEEE journal of solid-state circuits, 2009-08, Vol.44 (8), p.2222-2232
2009
Volltextzugriff (PDF)
Details
- Autor(en) / Beteiligte
- Titel
- A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme
- Ist Teil von
- IEEE journal of solid-state circuits, 2009-08, Vol.44 (8), p.2222-2232
- Ort / Verlag
- New York: IEEE
- Erscheinungsjahr
- 2009
- Quelle
- IEEE Electronic Library Online
- Beschreibungen/Notizen
- A 5-Gb/s/pin transceiver for DDR memory interface is proposed with a crosstalk suppression scheme. The proposed transceiver implements a staggered memory bus topology and a glitch canceller to suppress crosstalk-induced distortions in a memory channel. The transceiver is implemented using 0.18 mum CMOS process and operates at 5 Gb/s. The results demonstrate widened eye diagram and lower bit error rate. The eye width and height of the proposed scheme increases 28.3% and 11.1% compared to the conventional memory transceiver, respectively. The peak-to-peak jitter of output data is 52.82 ps.
- Sprache
- Englisch
- Identifikatoren
- ISSN: 0018-9200eISSN: 1558-173XDOI: 10.1109/JSSC.2009.2022303Titel-ID: cdi_ieee_primary_5173761
- Format
- –
- Schlagworte
- Cancellers, Channels, Circuits, CMOS, Couplings, Crosstalk, DDR, Distortion, glitch, Graphics, Impedance, Interference, Jitter, memory interface, Random access memory, signal integrity, staggered bus, Timing, Topology, transceiver, Transceivers