Details

Autor(en) / Beteiligte

• Lariviere, S.
• Picore, F.
• Saez, P.L.
• Baltzinger, J.-L.
• Delahaye, B.
• Matha, J.
• Gilhard, X.
• D'Oliveira, S.
• Lagarde, J.M.
• Prebot, J.L.
• Merlot, F.
• Nogueira, F.
• Petit, D.
• Williams, S.
• Besade, E.

Titel

Electro-static induced metal breakdown at interlayer dielectric post CMP brush clean process

Ist Teil von

• 2009 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 2009, p.17-21

Ort / Verlag

IEEE

Erscheinungsjahr

2009

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE/IET Electronic Library

Beschreibungen/Notizen

• During the introduction of a new product on an already qualified 0.25 mum technical node, wafer functional yields were found lower then expected compare to reference level. Basically, failing chips on TEM were showing an Electro-Static Discharge breakdown crack between two metal 2 lines. Process module partitioning and tool charging analysis pointed out the scrubber used to clean and dry wafers at the post interlayer dielectric chemical mechanical polishing step. Tool design analysis and process parameters experiments have been evaluated according to a new charging monitoring tool. Two alternate solutions have been found and confirmed at the end by functional yield recovery to technical node standard. This paper describes the investigation methodology from the earliest predictive failure analysis to the final manufacturing implemented fix that includes an innovative monitoring scheme.