Details

Autor(en) / Beteiligte

• Barke, E.
• Grabowski, D.
• Graeb, H.
• Hedrich, L.
• Heinen, S.
• Popp, R.
• Steinhorst, S.
• Yifan Wang

Titel

Formal approaches to analog circuit verification

Ist Teil von

• 2009 Design, Automation & Test in Europe Conference & Exhibition, 2009, p.724-729

Ort / Verlag

IEEE

Erscheinungsjahr

2009

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• For a speed-up of analog design cycles to keep up with the continuously decreasing time to market, iterative design refinement and redesigns are more than ever regarded as showstoppers. To deal with this issue, referred to as design and verification gap, the development of a continuous and consistent verification is mandatory. In digital design, formal verification methods are considered as a key technology for efficient design flows. However, industrial availability of formal methods for analog circuit verification is still negligible despite a growing need. In recent years, research institutions have made considerable advances in the area of formal verification of analog circuits. This paper presents a selection of four recent approaches in analog verification that cover a broad scope of verification philosophies.