Details

Autor(en) / Beteiligte

• Hyun-Woo Lee
• Won-Joo Yun
• Young-Kyoung Choi
• Hyang-Hwa Choi
• Jong-Jin Lee
• Ki-Han Kim
• Shin-Deok Kang
• Ji-Yeon Yang
• Jae-Suck Kang
• Hyeng-Ouk Lee
• Dong-Uk Lee
• Sujeong Sim
• Young-Ju Kim
• Won-Jun Choi
• Keun-Soo Song
• Sang-Hoon Shin
• Hyung-Wook Moon
• Seung-Wook Kwack
• Jung-Woo Lee
• Nak-Kyu Park
• Kwan-Weon Kim
• Young-Jung Choi
• Jin-Hong Ahn
• Byong-Tae Chung

Titel

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS

Ist Teil von

• 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.140-141,141a

Ort / Verlag

IEEE

Erscheinungsjahr

2009

Quelle

IEEE

Beschreibungen/Notizen

• We design PDLL that has a PLL and a DLL with different roles. The DLL, which is used for phase compensation, is digital with low power consumption. The PLL, which is used for jitter reduction, is a charge-pump type with dual K VCO and self-mode-shifting scheme, using an unregulated power supply for flexibility in operating range. Powering the PLL with an unregulated power supply is made possible by the power-noise- management technique of V PP control and by using a pseudo-rank architecture to suppress V DD noise due to low VPP pumping efficiency.