2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.128-129,129a
2009
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- Autor(en) / Beteiligte
- Titel
- 1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture
- Ist Teil von
- 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.128-129,129a
- Ort / Verlag
- IEEE
- Erscheinungsjahr
- 2009
- Quelle
- IEEE Electronic Library (IEL)
- Beschreibungen/Notizen
- As the workload and speed of a computer system increase, both the data bandwidth and capacity of main memory inevitably need to grow. However, the number of slots per channel is limited to maintain high bandwidth, making the capacity requirement difficult to meet. Another problem is that computer systems impose a limit on the supply of power since their power dissipation increases rapidly where main memories account for roughly 15% of total power consumption. To address these issues, we design a 4Gb DDR3 SDRAM that supports a 1.2 V supply voltage and 1.6 Gb/s data rate.
- Sprache
- Englisch
- Identifikatoren
- ISBN: 9781424434589, 1424434580ISSN: 0193-6530eISSN: 2376-8606DOI: 10.1109/ISSCC.2009.4977341Titel-ID: cdi_ieee_primary_4977341