IEEE journal of solid-state circuits, 2009-05, Vol.44 (5), p.1522-1530
2009
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Details
- Autor(en) / Beteiligte
- Titel
- A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces
- Ist Teil von
- IEEE journal of solid-state circuits, 2009-05, Vol.44 (5), p.1522-1530
- Ort / Verlag
- New York, NY: IEEE
- Erscheinungsjahr
- 2009
- Quelle
- IEEE Electronic Library (IEL)
- Beschreibungen/Notizen
- A DLL featuring jitter reduction techniques for a noisy environment is described. It controls a loop response mode by monitoring the magnitude of input jitter caused by supply noise. This technique varies the probability of phase error tracking. It reduces the output jitter of the DLL due to a low effective variance of input phase error and a narrow effective loop bandwidth. The DLL is implemented in a 0.13 mum CMOS process. Under noisy environments, the output clock of 1 GHz has 4.58 ps RMS and 29 ps peak-to-peak jitter.
- Sprache
- Englisch
- Identifikatoren
- ISSN: 0018-9200eISSN: 1558-173XDOI: 10.1109/JSSC.2009.2016993Titel-ID: cdi_ieee_primary_4907314
- Format
- –
- Schlagworte
- Applied sciences, Bandwidth, Circuit properties, Circuits, Circuits of signal characteristics conditioning (including delay circuits), Clocks, CMOS, Delay lines, delay-locked loop (DLL), Design. Technologies. Operation analysis. Testing, DRAM interface, Dynamic link libraries, Electric, optical and optoelectronic circuits, Electronic circuits, Electronics, Exact sciences and technology, Frequency synchronization, Integrated circuits, Integrated circuits by function (including memories and processors), Jitter, Monitoring, Noise reduction, Phase error, Phase noise, Random access memory, Reduction, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Tracking, Working environment noise