Details

Autor(en) / Beteiligte

• Fuse, T.
• Oowaki, Y.
• Terauchi, M.
• Watanabe, S.
• Yoshimi, M.
• Ohuchi, K.
• Matsunaga, J.

Titel

0.5 V SOI CMOS pass-gate logic

Ist Teil von

• 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC, 1996, p.88-89

Ort / Verlag

IEEE

Erscheinungsjahr

1996

Quelle

IEEE Xplore

Beschreibungen/Notizen

• Demand for low-power ULSIs for mobile electronic equipment is increasing rapidly. To reduce power consumption, lower operating voltage and minimized device size (or count) is essential. To lower the actual threshold voltage and lower the operation voltage, SOI MOSFET with gate-body connection is proposed. However, the circuit architecture that affords the maximum advantage of the body controlled SOI MOSFET has not yet been reported. The SOI CMOS pass-gate logic described here offers the lowest operation voltage and reduced transistor dimensions. In this logic the body of the SOI pass-gate is connected to the input signal given to the gate. Low threshold voltage for the onstate pass-gate and high threshold voltage for the off-state passgate is realized, and the increase in the threshold voltage due to the body-effect is suppressed. Two types of buffer suitable for SOI pass-gate logic are examined.