Details

Autor(en) / Beteiligte

• Nikam, V.
• Bhuwalka, K.K.
• Kottantharayil, A.

Titel

Optimization of n-channel tunnel FET for the sub-22nm gate length regime

Ist Teil von

• 2008 Device Research Conference, 2008, p.77-78

Ort / Verlag

IEEE

Erscheinungsjahr

2008

Quelle

IEEE/IET Electronic Library

Beschreibungen/Notizen

• In this work we explore for the first time, the design space for n-channel T-FETs with gate lengths below 22 nm using extensive device simulations. We show that the heterojunction tunnel-FET can satisfy ITRS requirements for HP and LSTP can be achieved using a SiGe-source device by an optimum choice of gate dielectric thickness and Ge fraction in Si 1-gamma Ge gamma .