Details

Autor(en) / Beteiligte

• Haran, B.S.
• Kumar, A.
• Adam, L.
• Chang, J.
• Basker, V.
• Kanakasabapathy, S.
• Horak, D.
• Fan, S.
• Chen, J.
• Faltermeier, J.
• Seo, S.
• Burkhardt, M.
• Burns, S.
• Halle, S.
• Holmes, S.
• Johnson, R.
• McLellan, E.
• Levin, T.M.
• Zhu, Y.
• Kuss, J.
• Ebert, A.
• Cummings, J.
• Canaperi, D.
• Paparao, S.
• Arnold, J.
• Sparks, T.
• Koay, C.S.
• Kanarsky, T.
• Schmitz, S.
• Petrillo, K.
• Kim, R.H.
• Demarest, J.
• Edge, L.F.
• Jagannathan, H.
• Smalley, M.
• Berliner, N.
• Cheng, K.
• LaTulipe, D.
• Koburger, C.
• Mehta, S.
• Raymond, M.
• Colburn, M.
• Spooner, T.
• Paruchuri, V.
• Haensch, W.
• McHerron, D.
• Doris, B.

Titel

22 nm technology compatible fully functional 0.1 μm2 6T-SRAM cell

Ist Teil von

• 2008 IEEE International Electron Devices Meeting, 2008, p.1-4

Ort / Verlag

IEEE

Erscheinungsjahr

2008

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• We demonstrate 22 nm node technology compatible, fully functional 0.1 mum 2 6T-SRAM cell using high-NA immersion lithography and state-of-the-art 300 mm tooling. The cell exhibits a static noise margin (SNM) of 220 mV at V dd =0.9 V. We also present a 0.09 mum 2 cell with SNM of 160 mV at V dd =0.9 V demonstrating the scalability of the design with the same layout. This is the world's smallest 6T-SRAM cell. Key enablers include band edge high-kappa metal gate stacks, transistors with 25 nm gate lengths, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts.