Details

Autor(en) / Beteiligte

• Van de Vel, H.
• Buter, B.
• van der Ploeg, H.
• Vertregt, M.
• Geelen, G.
• Paulus, E.

Titel

A 1.2V 250mW 14b 100MS/s digitally calibrated pipeline ADC in 90nm CMOS

Ist Teil von

• 2008 IEEE Symposium on VLSI Circuits, 2008, p.74-75

Ort / Verlag

IEEE

Erscheinungsjahr

2008

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• A 14 b pipeline ADC is realized in 90 nm CMOS at a 1.2 V supply. Enabling techniques are range-scaling in the first pipeline stage with charge-reset and digital background calibration of non-linearity. The ADC achieves 73 dB SNR and 91 dB SFDR at 100 MS/s sampling rate and 250 mW power consumption. The 73 dB SNDR performance is maintained within 3 dB up to a Nyquist input frequency and the FOM is 0.7 pJ/conv.