2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, 2008, p.143-146
2008
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Details
- Autor(en) / Beteiligte
- Titel
- Low power clocking strategies in deep submicron technologies
- Ist Teil von
- 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, 2008, p.143-146
- Ort / Verlag
- IEEE
- Erscheinungsjahr
- 2008
- Quelle
- IEL
- Beschreibungen/Notizen
- Recent silicon process technology advancements have given chip designers integration capabilities never were possible before, and have led to a new wave of complex ASICs (applied specific integrated circuits). These advanced processes come with new challenges. This paper presents some of the challenges in deep submicron technologies, which require new design practices. We demonstrate some issues related to clocking strategies and timing closure that were encountered during the design of a FEC40 ASIC, and a methodology is proposed to mitigate some of these issues. The FEC40 ASIC is a forward error correction chip designed for Nortelpsilas 40 Gb/s coherent optical transmission system. The chip has about 11 million gates at a core frequency of 350 MHz and has 70 clock domains. The chip was fabricated in a 90 nm technology.
- Sprache
- Englisch
- Identifikatoren
- ISBN: 9781424418107, 1424418100ISSN: 2381-3555eISSN: 2691-0462DOI: 10.1109/ICICDT.2008.4567265Titel-ID: cdi_ieee_primary_4567265
- Format
- –
- Schlagworte
- Application specific integrated circuits, Clock Gating, Clocks, deep submicron technologies, Delay effects, Integrated circuit interconnections, Integrated circuit technology, Manufacturing processes, On Chip Variation (OCV), Process design, Static Timing Analysis, Temperature, Timing, Voltage