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Test structure generation to quantify filling impact
Ist Teil von
2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2008, p.1-5
Ort / Verlag
IEEE
Erscheinungsjahr
2008
Quelle
IEEE Electronic Library (IEL)
Beschreibungen/Notizen
In present and future technology nodes, the insertion of metal filling can lead to timing yield losses. In this paper, we present a test structure generation method to study the impact of metal filling on interconnect timings. Such a method is mandatory when dealing with metal filling, because its insertion in real design does not follow standardized rules. The proposed test structure generation method is based on design of experiment (DOE) to minimize the number of structures. The DOE approach links test structures timings to filling pattern characteristics. This timing model is first validated by comparison with the test structures electrical simulations. Then the model is used for statistical analysis about filling impact depending on metal level.