Details

Autor(en) / Beteiligte

• Xuefeng Yu
• Dai, F.F.
• Irwin, J.D.
• Jaeger, R.C.

Titel

A 12 GHz 1.9 W Direct Digital Synthesizer MMIC Implemented in 0.18 \mum SiGe BiCMOS Technology

Ist Teil von

• IEEE journal of solid-state circuits, 2008-06, Vol.43 (6), p.1384-1393

Ort / Verlag

IEEE

Erscheinungsjahr

2008

Quelle

IEL

Beschreibungen/Notizen

• This paper presents a 12 GHz direct digital synthesizer (DDS) MMIC with 9-bit phase and 8-bit amplitude resolution implemented in a 0.18 mum SiGe BiCMOS technology. Composed of a 9-bit pipeline accumulator and an 8-bit sine-weighted current-steering DAC, the DDS is capable of synthesizing sinusoidal waveforms up to 5.93 GHz. The maximum clock frequency of the DDS MMIC is measured as 11.9 GHz at the Nyquist output and 12.3 GHz at 2.31 GHz output. The spurious-free dynamic range (SFDR) of the DDS, measured at Nyquist output with an 11.9 GHz clock, is 22 dBc. The power consumption of the DDS MMIC measured at a 12 GHz clock input is 1.9 W with dual power supplies of 3.3 V/4 V. The DDS thus achieves a record-high power efficiency figure of merit (FOM) of 6.3 GHz/W. With more than 9600 transistors, the active area of the MMIC is only 2.5 x 0.7 mm 2 . The chip was measured in packaged prototypes using 48-pin ceramic LCC packages.