Details

Autor(en) / Beteiligte

• Tan, Y.N.
• Wen, H.C.
• Park, C.
• Gilmer, D.C.
• Young, C.D.
• Heh, D.
• Sivasubramani, P.
• Huang, J.
• Majhi, P.
• Kirsch, P.D.
• Lee, B.H.
• Tseng, H.H.
• Jammy, R.

Titel

Tunnel Oxide Dipole Engineering in TANOS Flash Memory for Fast Programming with Good Retention and Endurance

Ist Teil von

• 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2008, p.54-55

Ort / Verlag

IEEE

Erscheinungsjahr

2008

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• Band engineering in TANOS (TaN-Al 2 O 3 -Si 3 N 4 -SiO 2 -Silicon) Flash memory utilizing an interfacial dipole is demonstrated for the first time. A dipole layer at the tunnel oxide/charge storage layer interface leads to increase in programming speed while maintaining good retention and endurance. Using a dipole layer results in a 40% increase in Va, shift at program voltage V g -V fb , = 11 V. The performance improvement by dipole incorporation into the TANOS stack is discussed.