Details

Autor(en) / Beteiligte

• Yun, Won-Joo
• Lee, Hyun Woo
• Shin, Dongsuk
• Kang, Shin Deok
• Yang, Ji Yeon
• Lee, Hyeng Ouk
• Lee, Dong Uk
• Sim, Sujeong
• Kim, Young Ju
• Choi, Won Jun
• Song, Keun Soo
• Shin, Sang Hoon
• Choi, Hyang Hwa
• Moon, Hyung Wook
• Kwack, Seung Wook
• Lee, Jung Woo
• Choi, Young Kyoung
• Park, Nak Kyu
• Kim, Kwan Weon
• Choi, Young Jung
• Ahn, Jin-Hong
• Yang, Ye Seok

Titel

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

Ist Teil von

• 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.282-613

Ort / Verlag

IEEE

Erscheinungsjahr

2008

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE Xplore

Beschreibungen/Notizen

• We design a DLL that has a slew-rate controlled duty-cycle-correction (DCC) with a fully digital controlled duty-cycle-error detector and has the update gear circuit to shift update mode for low power consumption. The DLL is composed of a dual loop and two types of digital DCC, at the input and output, which have a higher DCC capability when combined. We also design a clock receiver that generates a robust clock from a poor clock source.