Details

Autor(en) / Beteiligte

• Noori, A.M.
• Balseanu, M.
• Boelen, P.
• Cockburn, A.
• Demuynck, S.
• Felch, S.
• Gandikota, S.
• Gelatos, A.J.
• Khandelwal, A.
• Kittl, J.A.
• Lauwers, A.
• Wen-Chin Lee
• Jianxin Lei
• Mandrekar, T.
• Schreutelkamp, R.
• Shah, K.
• Thompson, S.E.
• Verheyen, P.
• Ching-Ya Wang
• Li-Qun Xia
• Arghavani, R.

Titel

Manufacturable Processes for \leq 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

Ist Teil von

• IEEE transactions on electron devices, 2008-05, Vol.55 (5), p.1259-1264

Ort / Verlag

IEEE

Erscheinungsjahr

2008

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• Manufacturable processes to reduce both channel and external resistances (R Ext ) in CMOS devices are described. Simulations show that R Ext will become equivalent to strained Si channel resistance near the 32-nm logic node. Tensile stress in plasma-enhanced chemical-vapor-deposited SiN x liners is increased with UV curing, boosting the NMOS drive current by 20% relative to a neutral reference. W contact-plug resistance (R c ) is reduced by 40% by optimizing preclean, liner/barrier, and nucleation steps. Replacing the fill material with Cu reduces R c by > 35% as compared to W. The Schottky barrier height of silicide contacts to p-Si is reduced by 0.12 eV with a 10% addition of Pt, resulting in a ~10% increase in the PMOS drive current. By implementing a two-step anneal process (spike + laser), the source/drain-extension resistance can be reduced by 20%.