Sie befinden Sich nicht im Netzwerk der Universität Paderborn. Der Zugriff auf elektronische Ressourcen ist gegebenenfalls nur via VPN oder Shibboleth (DFN-AAI) möglich. mehr Informationen...
Ergebnis 14 von 220

Details

Autor(en) / Beteiligte
Titel
Electrical Properties of Low-Temperature-Compatible P-Channel Polycrystalline-Silicon TFTs Using High- \kappa Gate Dielectrics
Ist Teil von
  • IEEE transactions on electron devices, 2008-04, Vol.55 (4), p.1027-1034
Ort / Verlag
New York, NY: IEEE
Erscheinungsjahr
2008
Quelle
IEEE Electronic Library Online
Beschreibungen/Notizen
  • In this paper, we describe a systematic study of the electrical properties of low-temperature-compatible p-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) using HfO 2 and HfSiO x , high-k gate dielectrics. Because of their larger gate capacitance density, the TFTs containing the high-k gate dielectrics exhibited superior device performance in terms of higher I on /I off current ratios, lower subthreshold swings (SSs), and lower threshold voltages (V th ), relative to conventional deposited-SiO 2 , albeit with slightly higher OFF-state currents. The TFTs incorporating HfSiO x , as the gate dielectric had ca. 1.73 times the mobility (mu FE ) relative to that of the deposited-SiO 2 TFTs; in contrast, the HfO 2 TFTs exhibited inferior mobility. We investigated the mechanism for the mobility degradation in these HfO 2 TFTs. The immunity of the HfSiO x , TFTs was better than that of the HfO 2 TFTs-in terms of their V th shift, SS degradation, mu FE degradation, and drive current deterioration-against negative bias temperature instability stressing. Thus, we believe that HfSiO x , rather than HfO 2 , is a potential candidate for use as a gate-dielectric material in future high-performance poly-Si TFTs.

Weiterführende Literatur

Empfehlungen zum selben Thema automatisch vorgeschlagen von bX