Details

Autor(en) / Beteiligte

• Lee, J.I.
• Park, H.
• Cho, S.L.
• Park, Y.L.
• Bae, B.J.
• Park, J.H.
• Park, J.S.
• An, H.G.
• Bae, J.S.
• Ahn, D.H.
• Kim, Y.T.
• Horii, H.
• Song, S.A.
• Shin, J.C.
• Park, S.O.
• Kim, H.S.
• U-In Chung
• Moon, J.T.
• Ryu, B.I.

Titel

Highly Scalable Phase Change Memory with CVD GeSbTe for Sub 50nm Generation

Ist Teil von

• 2007 IEEE Symposium on VLSI Technology, 2007, p.102-103

Ort / Verlag

IEEE

Erscheinungsjahr

2007

Quelle

IEEE Xplore

Beschreibungen/Notizen

• first present a PRAM with confinement of chemically vapor deposited GeSbTe (CVD GST) within high aspect ratio 50nm contact for sub 50nm generation PRAMs. By adopting confined GST, we were able to reduce the reset current below ~260μA and thermally stable CVD Ge 2 Sb 2 Te 5 compound having hexagonal phase was uniformly filled in a contact while maintaining constant composition along with 150nm depth. Our results indicate that the confined cell structure of 50nm contact is applicable to PRAM device below 50 nm design rule due to small GST size based on small contact and direct top electrode contact, reduced reset current, minimized etch damage, and low thermal disturbance effect.