IEEE transactions on electron devices, 2007-09, Vol.54 (9), p.2466-2474
2007
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Details
- Autor(en) / Beteiligte
- Titel
- Impact of Line-Edge Roughness on FinFET Matching Performance
- Ist Teil von
- IEEE transactions on electron devices, 2007-09, Vol.54 (9), p.2466-2474
- Ort / Verlag
- New York, NY: IEEE
- Erscheinungsjahr
- 2007
- Quelle
- IEEE Xplore
- Beschreibungen/Notizen
- As a result of CMOS scaling, the critical dimension (CD) of integrated circuits has been shrinking. At sub-45 nm nodes, in which FinFET is a viable device architecture, line-edge roughness (LER) in current Si-based technologies forms a significant fraction of the line CD. In such cases, analyzing the impact of LER on FinFET performance is vital for meeting various device specifications. The impact of LER on the matching performance of FinFETs is investigated through statistical device simulations, comparing the relative importance of fin- and gate-LER. Fin-LER is shown to significantly degrade FinFET matching performance under DC and transient operations. Combining our device simulation results with experimental data, it is shown that fin-LER will dominate the intra-bit-cell stochastic mismatch in FinFET static random access memories at the LSTP-32-nm node. The electrical performance of spacer-defined fin (SDF) and resist-defined fin (RDF) patterning technologies has been compared. It is shown that, with respect to RDF patterning, the spacer-defined process has the potential to improve FinFET matching performance by 90%.
- Sprache
- Englisch
- Identifikatoren
- ISSN: 0018-9383eISSN: 1557-9646DOI: 10.1109/TED.2007.902166Titel-ID: cdi_ieee_primary_4294184
- Format
- –
- Schlagworte
- Applied sciences, CMOS, CMOS technology, Computational modeling, Design. Technologies. Operation analysis. Testing, Devices, Electric potential, Electronics, Exact sciences and technology, FinFET, FinFETs, fully depleted silicon-on-insulator (FDSOI), Integrated circuits, Integrated circuits by function (including memories and processors), line-edge roughness (LER), Logic gates, Matching, Microelectronic fabrication (materials and surfaces technology), Microelectronics, Patterning, Performance evaluation, Random access memory, Resource description format, Roughness, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Simulation, spacer-defined patterning, Specifications, Studies, transistor matching, Transistors