Details

Autor(en) / Beteiligte

• Thapliyal, H.
• Arabnia, H.R.
• Vinod, A.P.

Titel

Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible Logic Implementation

Ist Teil von

• 2006 49th IEEE International Midwest Symposium on Circuits and Systems, 2006, Vol.2, p.438-442

Ort / Verlag

IEEE

Erscheinungsjahr

2006

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• In this paper, the authors propose the idea of a combined integer and floating point multiplier (CIFM) for FPGAs. The authors propose the replacement of existing 18times18 dedicated multipliers in FPGAs with dedicated 24times24 multipliers designed with small 4times4 bit multipliers. It is also proposed that for every dedicated 24times24 bit multiplier block designed with 4times4 bit multipliers, four redundant 4times4 multiplier should be provided to enforce the feature of self repairability (to recover from the faults). In the proposed CIFM reconfigurability at run time is also provided resulting in low power. The major source of motivation for providing the dedicated 24times24 bit multiplier stems from the fact that single precision floating point multiplier requires 24times24 bit integer multiplier for mantissa multiplication. A reconfigurable, self-repairable 24times24 bit multiplier (implemented with 4times4 bit multiply modules) will ideally suit this purpose, making FPGAs more suitable for integer as well floating point operations. A dedicated 4times4 bit multiplier is also proposed in this paper. Moreover, in the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. Thus, this paper also paper provides the reversible logic implementation of the proposed CIFM. The reversible CIFM designed and proposed here will form the basis of the completely reversible FPGAs.