Details

Autor(en) / Beteiligte

• Wang, G.
• Cheng, K.
• Ho, H.
• Faltermeier, J.
• Kong, W.
• Kim, H.
• Cai, J.
• Tanner, C.
• McStay, K.
• Balasubramanyam, K.
• Pei, C.
• Ninomiya, L.
• Li, X.
• Winstel, K.
• Dobuzinsky, D.
• Naeem, M.
• Zhang, R.
• Deschner, R.
• Brodsky, M.J.
• Allen, S.
• Yates, J.
• Feng, Y.
• Marchetti, P.
• Norris, C.
• Casarotto, D.
• Benedict, J.
• Kniffm, A.
• Parise, D.
• Khan, B.
• Barth, J.
• Parries, P.
• Kirihata, T.
• Norum, J.
• Iyer, S.S.

Titel

A 0.127 μm2 High Performance 65nm SOI Based embedded DRAM for on-Processor Applications

Ist Teil von

• 2006 International Electron Devices Meeting, 2006, p.1-4

Ort / Verlag

IEEE

Erscheinungsjahr

2006

Quelle

IEEE Xplore Digital Library

Beschreibungen/Notizen

• The authors present a 65nm embedded DRAM cell (0.127 μm 2 cell size) on unpatterned SOI fabricated using standard high performance SOI technology with dual stress liner (DSL). The cell utilizes a low-leakage 2.2-nm gate oxide pass transistor and a deep trench capacitor. A trench side wall spacer process enables a simplified collarless process. Connection to the buried plate is realized by silicided substrate guardrings with fully landed tungsten contacts. The bitline structure and the deep trench capacitor are designed for high transfer ratio and low RC constant which ensure high performance and sufficient sensing signal. The pass transistor is strain engineered to boost on current and employs optimized S/D junctions to help attain sub-pA off current. This technology has produced fully-functional 2Mb prototype embedded macros with sub-1.5ns latency and sub-2ns random cycle times for on-processor caches. The low leakage device developed also enables for the first time a low standby power SOI technology