Details

Autor(en) / Beteiligte

• Shih, J.r.
• Tsui, R.f.
• Liu, Kevin
• Tsai, Y.s.
• Chin, H.w.
• Wu, Kenneth

Titel

A New Phenomenon of Retention Time Evolution in Embedded DRAM Technology with High-K Dielectrics (Ta2O5) MIM Capacitor After HTOL Test

Ist Teil von

• 2006 IEEE International Reliability Physics Symposium Proceedings, 2006, p.703-704

Ort / Verlag

IEEE

Erscheinungsjahr

2006

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• In this paper, a new phenomenon regarding to failure bit count (FBC) distribution and data retention time of embedded DRAM with high-K dielectric Ta 2 O 5 MIM capacitors has been observed and explored. Different from conventional knowledge with FBC increase or retention time reduction of DRAM after burn-in, it is found FBC decreased and retention time increased in the sub-0.1mum embedded DRAM technology with high-K dielectric Ta 2 O 5 MIM capacitors. Although the band-to-defect tunneling (BDT) induced junction leakage currents of cell transistors under hot carrier injection (HCI) and off-state bias-temperature (BT) stress will be enhanced, which degrade the FBC and retention time performance. However, it was found the leakage current reduction of high-K dielectric Ta 2 O 5 capacitor after burn-in dominates the FBC reduction and retention time increase