Details

Autor(en) / Beteiligte

• Palaskas, Y.
• Ravi, A.
• Pellerano, S.
• Carlton, B.R.
• Elmala, M.A.
• Bishop, R.
• Banerjee, G.
• Nicholls, R.B.
• Ling, S.K.
• Dinur, N.
• Taylor, S.S.
• Soumyanath, K.

Titel

A 5-GHz 108-Mb/s 2 \times2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm Power Amplifiers in 90-nm CMOS

Ist Teil von

• IEEE journal of solid-state circuits, 2006-12, Vol.41 (12), p.2746-2756

Ort / Verlag

IEEE

Erscheinungsjahr

2006

Quelle

IEEE Xplore

Beschreibungen/Notizen

• Multiple antenna transceivers combined with MIMO signal processing offer the potential for increased data rates and/or range in wireless systems. This paper presents a fully integrated 5-GHz 2times2 MIMO WLAN transceiver RFIC implemented in 90-nm CMOS. The paper identifies the key MIMO integration issues and proposes techniques to optimize MIMO performance. It is shown that crosstalk between the multiple transceivers residing on the same die can degrade MIMO performance and has to be carefully minimized, especially when power amplifiers are integrated on-die. A shared LO generation and distribution network is designed to maximize MIMO phase noise immunity without introducing undesired crosstalk. The fabricated MIMO receiver achieves a sensitivity of -63 dBm while receiving 108Mb/s in MIMO spatial multiplexing mode in the presence of a 25-ns Rayleigh fading channel. The sensitivity of a single receiver in the presence of AWGN noise is -76 dBm. Linearized 3.3-V 5-GHz power amplifiers with P 1dB =20.5 \ dBm deliver an average power of +13/+16 dBm each, in MIMO/SISO modes respectively (EVM=-27/-25 dB). The measured performance demonstrates the effectiveness of the isolation techniques employed. The system in a package includes an 18 mm 2 die and microstrip front-end matching networks implemented on a flip-chip package