Details

Autor(en) / Beteiligte

• Al-Qutayri, M.A.
• Al-Araji, S.R.
• Al-Moosa, N.I.

Titel

Improved First-Order Time-Delay Tanlock Loop Architectures

Ist Teil von

• IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-09, Vol.53 (9), p.1896-1908

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2006

Quelle

IEEE/IET Electronic Library

Beschreibungen/Notizen

• This paper presents a study of the performance of the first-order time-delay digital tanlock loop (TDTL). It proposes a number of modified loop architectures that overcome some of the original TDTL design limitations. Simulation results indicate that the new architectures, which include delay switching, gain adaptation and a combination of both techniques, improve the TDTL performance in terms of acquisition speed, locking range and resilience to frequency disturbances. The first-order TDTL was also implemented on a field programmable gate array (FPGA). The real-time results from the FPGA implementation are in agreement with the ones obtained through simulation