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Submicron CMOS technologies provide well-established solutions to the implementation of low noise front-end electronics for a wide range of detector applications. In recent years high performance mixed signal circuits were fabricated in 0.35 mum and 0.25 mum processes. Presently the IC designers' effort is gradually shifting to 0.13 mum technologies, following the trend of commercial silicon foundries. Since commercial CMOS processes maintain a steady trend in device scaling, it is essential to monitor the impact of these technological advances on the noise parameters of the devices. To estimate the noise limits of a front-end system in the 0.13 mum node, this work presents the results of noise measurements carried out on NMOS and PMOS devices in two commercial processes from different foundries. The behavior of the 1/f and white noise terms is studied as a function of the device polarity and of the gate length and width to account for different detector requirements. The study is focused on low current density applications where devices are biased in weak or moderate inversion. Data obtained from the measurements provide a powerful tool to model noise parameters and establish front-end design criteria in a 0.13 mum CMOS process