IEEE electron device letters, 2006-05, Vol.27 (5), p.412-415
2006
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Details
- Autor(en) / Beteiligte
- Titel
- Observation of suppressed interface state relaxation under positive gate biasing of the ultrathin oxynitride gate p-MOSFET subjected to negative-bias temperature stressing
- Ist Teil von
- IEEE electron device letters, 2006-05, Vol.27 (5), p.412-415
- Ort / Verlag
- New York, NY: IEEE
- Erscheinungsjahr
- 2006
- Quelle
- IEL
- Beschreibungen/Notizen
- The impact of a positive gate relaxation voltage on the recovery of an ultrathin oxynitride gate p-MOSFET subjected to negative-bias temperature stressing is investigated. Apart from reaffirming previous observations on the accelerated threshold voltage recovery due primarily to positive field-induced discharge of positive SiO/sub 2/ bulk states, the results also unambiguously show that the relaxation of Si/SiO/sub 2/ interface states (N/sub it/) is suppressed. The observed suppression of N/sub it/ relaxation poses an important challenge to the existing viewpoint of increased N/sub it/ relaxation under positive gate biasing.
- Sprache
- Englisch
- Identifikatoren
- ISSN: 0741-3106eISSN: 1558-0563DOI: 10.1109/LED.2006.873878Titel-ID: cdi_ieee_primary_1626473
- Format
- –
- Schlagworte
- Acceleration, Applied sciences, Character generation, Charge pumping current, Degradation, Dielectric measurements, Electric potential, Electronics, Exact sciences and technology, Gates, hole trapping, Interface states, Interfaces, MOSFET circuits, negative-bias temperature instability (NBTI), nitrided oxide, oxynitride, Oxynitrides, Plasma measurements, Recovery, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Silicon dioxide, SiON, Stress measurement, Stress relaxation, Stressing, Temperature, Threshold voltage, Transistors, Voltage