Details

Autor(en) / Beteiligte

• Bell, R.H.
• Bhatia, R.R.
• John, L.K.
• Stuecheli, J.
• Griswell, J.
• Tu, P.
• Capps, L.
• Blanchard, A.
• Thai, R.

Titel

Automatic testcase synthesis and performance model validation for high performance PowerPC processors

Ist Teil von

• 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006, p.154-165

Ort / Verlag

IEEE

Erscheinungsjahr

2006

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• The latest high-performance IBM PowerPC microprocessor, the POWERS chip, poses challenges for performance model validation. The current state-of-the-art is to use simple hand-coded bandwidth and latency testcases, but these are not comprehensive for processors as complex as the POWER5 chip. Applications and benchmark suites such as SPEC CPU are difficult to set up or take too long to execute on functional models or even on detailed performance models. We present an automatic testcase synthesis methodology to address these concerns. By basing testcase synthesis on the workload characteristics of an application, source code is created that largely represents the performance of the application, but which executes in a fraction of the runtime. We synthesize representative PowerPC versions of the SPEC2000, STREAM, TPC-C and Java benchmarks, compile and execute them, and obtain an average IPC within 2.4% of the average IPC of the original benchmarks and with many similar average workload characteristics. The synthetic testcases often execute two orders of magnitude faster than the original applications, typically in less than 300K instructions, making performance model validation for today's complex processors feasible.