Details

Autor(en) / Beteiligte

• Wagdy, M.F.
• Vaishnava, S.

Titel

A Fast-Locking Digital Phase-Locked Loop

Ist Teil von

• Third International Conference on Information Technology: New Generations (ITNG'06), 2006, p.742-746

Ort / Verlag

IEEE

Erscheinungsjahr

2006

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE Xplore

Beschreibungen/Notizen

• A conventional digital phase-locked loop (DPLL) is designed using (Baker et al., 2003) to operate at 1GHz using 0.18 mum CMOS technology; its lock time is 4.19 mus. By adding a coarse/fine tuning control unit composed of a digital-to-analog converter (DAC) and a counter as well as switching the currents of the charge pump, a fast-locking DPLL results, with a lock time of 1.02 mus, i.e. an improvement by a factor of 4. Simulations for both DPLLs verified the performance improvement due to using a fast-locking technique