2005 6th International Conference on ASIC, 2005, Vol.1, p.317-320
2005
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Details
- Autor(en) / Beteiligte
- Titel
- A low-power complementary pass-transistor tree multiplier based on adiabatic 4-2 compressors
- Ist Teil von
- 2005 6th International Conference on ASIC, 2005, Vol.1, p.317-320
- Ort / Verlag
- IEEE
- Erscheinungsjahr
- 2005
- Quelle
- IEEE Electronic Library (IEL)
- Beschreibungen/Notizen
- This paper describes a low-power tree multiplier based on adiabatic logic. It is composed of three parts: a partial-product generator, a partial-product compression tree (Wallace tree), and a final carry-lookahead adder. Adiabatic 4-2 compressors are used to construct the Wallace tree. All the circuits use complementary pass-transistor adiabatic logic (CPAL) circuits to recover the charge of node capacitances. The simulation results show that the CPAL tree multiplier achieves considerable energy savings.
- Sprache
- Englisch
- Identifikatoren
- ISBN: 9780780392106, 0780392108ISSN: 2162-7541eISSN: 2162-755XDOI: 10.1109/ICASIC.2005.1611302Titel-ID: cdi_ieee_primary_1611302
- Format
- –
- Schlagworte
- Circuit simulation, CMOS logic circuits, Compressors, Energy loss, Logic arrays, Logic circuits, Logic design, MOSFETs, Parasitic capacitance, Voltage