Details

Autor(en) / Beteiligte

• Kromer, C.
• Sialm, G.
• Berger, C.
• Morf, T.
• Schmatz, M.L.
• Ellinger, F.
• Erni, D.
• Bona, G.-L.
• Jackel, H.

Titel

A 100-mW 4/spl times/10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects

Ist Teil von

• IEEE journal of solid-state circuits, 2005-12, Vol.40 (12), p.2667-2679

Ort / Verlag

IEEE

Erscheinungsjahr

2005

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• This paper describes a quad optical transceiver for low-power high-density short-distance optical data communication. Each channel transmits 10 Gb/s over a multimode (MM) fiber and features a link margin of 5.2 dB at a bit error rate (BER) of 10/sup -12/. The transmit and receive amplifying circuits are implemented in an 80-nm digital CMOS process. Each driver consumes 2 mW from a 0.8-V supply, and each vertical cavity surface-emitting laser (VCSEL) requires 7 mA from a 2.4-V supply. The receiver excluding the output buffer consumes 6 mW from a 1.1-V supply per channel and achieves a transimpedance gain of 80.1 dB/spl Omega/. The isolation to the neighboring channels is >30dB including the bond wires and optical components. A detailed link budget analysis takes the relevant system impairments as losses and power penalties into account, derives the specifications for the electrical circuits, and accurately predicts the link performance. This work presents the highest serial data rate for CMOS transceiver arrays and the lowest power consumption per data rate reported to date.