Details

Autor(en) / Beteiligte

• Thean, A.V.Y.
• White, T.
• Sadaka, M.
• McCormick, L.
• Ramon, M.
• Mora, R.
• Beckage, P.
• Canonico, M.
• Wang, X.-D.
• Zollner, S.
• Murphy, S.
• Van Der Pas, V.
• Zavala, M.
• Noble, R.
• Zia, O.
• Kang, L.-G.
• Kolagunta, V.
• Cave, N.
• Cheek, J.
• Mendicino, M.
• Nguyen, B.-Y.
• Orlowski, M.
• Venkatesan, S.
• Mogab, J.
• Chang, C.H.
• Chiu, Y.H.
• Tuan, H.C.
• See, Y.C.
• Liang, M.S.
• Sun, Y.C.
• Cayrefourcq, I.
• Metral, F.
• Kennard, M.
• Mazure, C.

Titel

Performance of super-critical strained-Si directly on insulator (SC-SSOI) CMOS based on high-performance PD-SOI technology

Ist Teil von

• Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005, 2005, p.134-135

Ort / Verlag

IEEE

Erscheinungsjahr

2005

Quelle

IEEE Xplore

Beschreibungen/Notizen

• This paper describes the performance of multiple-V/sub T/, Triple-gate oxide SC-SSOI CMOS realized with Freescale's high-performance silicon-on-insulator (HiPerMOS-SOI) and SOITEC's advanced wafer-bonding technology. The thermal stability of wafer-bonded strained substrate, the beneficial impact of biaxial strain on gate-leakage and SC-SSOI enhanced SRAM bitcell operation are demonstrated for the first time. In-addition, the important scaling issues due to parasitic resistance and channel strain engineering are identified.