Details

Autor(en) / Beteiligte

• Chang, L.
• Fried, D.M.
• Hergenrother, J.
• Sleight, J.W.
• Dennard, R.H.
• Montoye, R.K.
• Sekaric, L.
• McNab, S.J.
• Topol, A.W.
• Adams, C.D.
• Guarini, K.W.
• Haensch, W.

Titel

Stable SRAM cell design for the 32 nm node and beyond

Ist Teil von

• Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005, 2005, p.128-129

Ort / Verlag

IEEE

Erscheinungsjahr

2005

Quelle

IEEE Xplore

Beschreibungen/Notizen

• SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. 6T-SRAM can be optimized for stability by choosing the cell layout, device threshold voltages, and the /spl beta/ ratio. 8T-SRAM, however, provides a much greater enhancement in stability by eliminating cell disturbs during a read access, thus facilitating continued technology scaling. We demonstrate the smallest 6T (0.124/spl mu/m/sup 2/ half-cell) and full 8T (0.1998/spl mu/m/sup 2/) cells to date.