Details

Autor(en) / Beteiligte

• Bhuwalka, K.K.
• Schulze, J.
• Eisele, I.

Titel

Scaling issues of n-channel vertical tunnel FET with /spl delta/p/sup +/ SiGe layer

Ist Teil von

• Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC, 2004, p.215-216 vol.1

Ort / Verlag

IEEE

Erscheinungsjahr

2004

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• The performance of a n-channel vertical tunnel field-effect transistor is shown to improve significantly by bandgap engineering at the tunneling junction. The bandgap modulation is achieved by inserting a heavily doped 3 nm delta SiGe layer at the p-source end. Since the bandgap at the tunneling junction determines the tunneling barrier height, having a SiGe delta layer results in lowering it. Thereby, increasing the tunneling probability under similar bias conditions. We show that controlling the Ge mole fraction, x, in SiGe, gives an additional parameter for control of device performance. Device on-current, I/sub on/, and threshold voltage, V/sub T/, are seen to improve considerably. However, as the device is scaled down, the tunneling probability increases significantly even for V/sub GS/=0 V as x is increased. Thereby, leading to large increase in tunneling leakage current. Optimization of the device performance can then be done by appropriate choice of x with gate oxide thickness, t/sub ox/, according to technology requirements.