Details

Autor(en) / Beteiligte

• Jin Cai
• Kumar
• Steigerwalt
• Ho
• Schonenberg
• Stein
• Huajie Chen
• Jenkins
• Qiqing Ouyang
• Oldiges
• Tak Ning

Titel

Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate

Ist Teil von

• 2003 Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (IEEE Cat. No.03CH37440), 2003, p.215-218

Ort / Verlag

IEEE

Erscheinungsjahr

2003

Quelle

IEEE Explore

Beschreibungen/Notizen

• We present a comprehensive study of the DC, RF and circuit performance of vertical SiGe-base npn bipolar transistors on 120nm SOI. It includes the sensitivity of device performance to collector doping N/sub C/, layout, and SOI substrate bias. At large positive substrate bias, measured peak f/sub T/, f/sub MAX/ and ECL ring oscillator speed for nominal 180nm devices are 60GHz, 57GHz and 20psec for N/sub C/=1.5/spl times/10/sup 17//cm/sup 3/ respectively, and 71GHz, 54GHz and 18psec for N/sub C/=4.8/spl times/10/sup 17//cm/sup 3/ respectively. Projected f/sub T/ for a scaled 100nm device on 55nm SOI approaches 200GHz.