Details

Autor(en) / Beteiligte

• De Salvo, B.
• Gerardi, C.
• Lombardo, S.
• Baron, T.
• Perniola, L.
• Mariolle, D.
• Mur, P.
• Toffoli, A.
• Gely, M.
• Semeria, M.N.
• Deleonibus, S.
• Ammendola, G.
• Ancarani, V.
• Melanotte, M.
• Bez, R.
• Baldi, L.
• Corso, D.
• Crupi, I.
• Puglisi, R.A.
• Nicotra, G.
• Rimini, E.
• Mazen, F.
• Ghibaudo, G.
• Pananakakis, G.
• Compagnoni, C.M.
• Ielmini, D.
• Lacaita, A.
• Spinelli, A.
• Wan, Y.M.
• van der Jeugd, K.

Titel

How far will silicon nanocrystals push the scaling limits of NVMs technologies?

Ist Teil von

• IEEE International Electron Devices Meeting 2003, 2003, p.26.1.1-26.1.4

Ort / Verlag

IEEE

Erscheinungsjahr

2003

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.