2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC, 2003, p.300-494 vol.1
2003
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Details
- Autor(en) / Beteiligte
- Titel
- A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM
- Ist Teil von
- 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC, 2003, p.300-494 vol.1
- Ort / Verlag
- IEEE
- Erscheinungsjahr
- 2003
- Quelle
- IEL
- Beschreibungen/Notizen
- A 1.2 V 72 Mb DDR3 SRAM in a 0.10 /spl mu/m CMOS process achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines reduce the power dissipation and the number of data lines by half. Clocks phase-shifted by 0/spl deg/, 90/spl deg/ and 270/spl deg/ are generated by clock adjustment circuits. On-chip input termination with linearity of /spl plusmn/4.1% is developed to improve signal integrity at higher data rates.
- Sprache
- Englisch
- Identifikatoren
- ISBN: 0780377079, 9780780377073ISSN: 0193-6530eISSN: 2376-8606DOI: 10.1109/ISSCC.2003.1234307Titel-ID: cdi_ieee_primary_1234307
- Format
- –
- Schlagworte
- Clocks, CMOS process, Delay, Differential amplifiers, Driver circuits, Mirrors, Power dissipation, Random access memory, Sampling methods, Timing