Details

Autor(en) / Beteiligte

• Henrique, L.
• Ferreira, C.
• Moreno, R.L.
• Pimenta, T.C.
• Filho, C.A.R.

Titel

A precise sample-and-hold circuit topology in CMOS for low voltage applications with offset voltage self correction

Ist Teil von

• IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions, 2002, Vol.2, p.914-917 vol.2

Ort / Verlag

IEEE

Erscheinungsjahr

2002

Quelle

IEEE Xplore

Beschreibungen/Notizen

• This work describes a new topology for CMOS sample-and-hold circuits in low voltage with self-correction of the offset voltage caused by mismatches in the differential input pair of the operational amplifier. The charge injection of the NMOS switches, although not properly modeled by the simulators, is an important factor and it is minimized in this topology. The results were obtained using the ACCUSIM II simulator on the AMS CMOS 0.8 /spl mu/m CYE and they reveal the circuit has a reduced error of just 0.03% at the output.