Details

Autor(en) / Beteiligte

• Nani, C.
• Monaco, E.
• Ghittori, N.
• Bosi, A.
• Albano, D.
• Asero, C.
• Codega, N.
• Di Pasquo, A.
• Fabiano, I.
• Garampazzi, M.
• Giunco, F.
• Burgos, D.
• Minoia, G.
• Rossi, P.
• Sosio, M.
• Vignoli, L.
• Temporiti, E.
• Scouten, S.
• Jantzi, S.

Titel

A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz

Ist Teil von

• 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

Ort / Verlag

IEEE

Erscheinungsjahr

2024

Quelle

IEEE Xplore

Beschreibungen/Notizen

• We present a 60GS/s 7b 64-way Time Interleaved (TI) ADC with Analog Front End that features a non binary Partial Loop Unrolled (LU) SAR SubADC architecture which enables optimum comparator noise and power trade off. Comparator offsets among comparators of each SubADC are calibrated in background without analog hardware overhead by detecting patterns in the SAR output decisions. Fabricated in 5nm technology, the prototype AFE and ADC delivers 34.3dB SNDR till 32GHz and draws 109.3mW from 0.9V supply.