Details

Autor(en) / Beteiligte

• Shadangi, Ashish Ranjan
• Das, Suvra Sekhar
• Chakrabarti, Indrajit

Titel

Low-Complexity VLSI Architecture for OTFS Transceiver Under Multipath Fading Channel

Ist Teil von

• IEEE transactions on very large scale integration (VLSI) systems, 2024-07, Vol.32 (7), p.1285-1296

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2024

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• Orthogonal time frequency space (OTFS) modulation has established itself as a dependable protocol for high-speed vehicular communication. This pioneering technique operates within a novel 2-D delay-Doppler domain waveform. When compared with conventional modulation methods like orthogonal frequency-division multiplexing (OFDM), OTFS demonstrates superior performance enhancements in scenarios involving rapidly moving wireless channels. This article begins by initially unveiling the input-output association of the OTFS signal within the delay-time domain. A comprehensive comparison with the established OFDM waveform highlights the potential of OTFS for achieving a notably lower bit error rate (BER) under various conditions, which has been obtained by using the minimum mean square equalizer (MMSE) equalization technique. Finally, we have proposed a novel and low-complexity VLSI architecture for the OTFS transmitter and the receiver by using the lower-upper (LU) decomposition technique for the first time in the literature. We have compared the performance metrics of our proposed transmitter architecture with the existing work, where our design works 7.394% faster than others, utilizing 89.354% less in the number of lookup tables (LUTs) and 79.984% less in the number of flip-flops (FFs), which shows that our design is more optimized in latency and resource utilization. There is no architecture design of the OTFS receiver part in the existing literature to compare; we have shown the resource utilization of our proposed receiver architecture for the first time in the literature, followed by timing analysis and functionality testing of the proposed architecture.