Details

Autor(en) / Beteiligte

• Xu, Dingxin
• Liu, Zezheng
• Kuai, Yifeng
• Huang, Hongye
• Zhang, Yuncheng
• Sun, Zheng
• Liu, Bangan
• Wang, Wenqian
• Xiong, Yuang
• Qiu, Junjun
• Madany, Waleed
• Zhang, Yi
• Fadila, Ashbir Aviat
• Shirane, Atsushi
• Okada, Kenichi

Titel

10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter

Ist Teil von

• 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.192-194

Ort / Verlag

IEEE

Erscheinungsjahr

2024

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• Modern wireless transceivers and FMCW radar systems are demanding stringent specifications on PLL integrated jitter and spur performance for lower EVM and higher position accuracy. To achieve lower jitter, a digital-to-time converter (DTC) is usually used in fractional-N PLLs to cancel the quantization noise (QN) from delta-sigma modulation (DSM), which is used to control the multi-modulus divider (MMD) [1]. However, the integral non-linearity (INL) of DTCs causes periodic patterns at the input of the phase detector (PD), leading to fractional spurs. Some conventional PLLs use dither to mitigate the fractional spur problem [2-4]. Although the dither-based techniques show a strong suppression in fractional spurs, the power of those spurs still remains in the form of random noise, limiting the reduction in integrated jitter. On the other hand, digital pre-distortion (DPD) can be used to suppress fractional spur power without increasing random noise by compensating the DTC INLs [5, 6]. Unfortunately, extra time is needed for INL lookup tables to update, resulting in longer PLL locking time. In order to simultaneously achieve a low fractional-spur level and a low integrated jitter without increasing the PLL locking time, this work presents a PLL with a cascaded-fractional divider technique and a pseudo-differential-DTC technique that can achieve -62.1dBc worst-case fractional spur and 143.7fs integrated jitter.